This datasheet describes synchronous pipeline mode, high-performance CMOS static random access memories (SRAMs) with 8Mb (256Kx36 & 512×18) and 4Mb (128Kx36 & 256Kx18) organizations.
The SRAMs feature registered outputs, common I/O, and asynchronous output enable. They operate on a single +2.5V power supply and are compatible with HSTL I/O interfaces.
Key Features:
• 0.25 micron CMOS technology
• Synchronous pipeline mode of operation with self-timed late write
• Single differential HSTL clock
• Boundary scan using limited set of JTAG 1149.1 functions
• Byte write capability and global write enable
• 7 x 17 Bump Ball Grid Array package with SRAM JEDEC standard pinout and boundary scan order
Manual:
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