ZiLOG Z80 CTC Counter/Timer Circuit Datasheet

Category: Electronics, Microprocessors Microcontrollers Peripheral ICS, Zilog

Overview

The ZiLOG Z80 CTC (Counter/Timer Circuit) provides four independently programmable counter/timer channels ideal for microcomputer system applications requiring event counting, interrupt and interval timing, and clock rate generation. Each channel comes with a downcounter, configurable 16 or 256 prescaler, and automatic reload at zero count, with three channels featuring Zero Count/Timeout outputs. The datasheet covers NMOS (20843004 MHz, 20843006 MHz) and CMOS (28C3006 DC to 6.17 MHz, 784C3008 DC to 8 MHz, 284C3010 – DC to 10 MHz) versions, addressing design needs for cost efficiency and low power consumption, respectively.

Compatibility and Performance

The Z80 CTC offers seamless integration with the Z80 CPU and Z80 SIO for baud rate generation and uses the standard Z80 family daisy-chain interrupt structure for fully vectored prioritized interrupts without additional logic. The 6 MHz version is optimized to support a 6.144 MHz CPU clock operation. Only a single +5% V power supply and the standard Z80 single-phase system clock are required.

Features and Functional Description

Key features include selectable positive or negative triggering of timer operations and the capability to drive Darlington transistors directly. The CTC’s four channels provide a simplified system design that minimizes the need for external logic. Programmability is straightforward; each channel is set using two words—a control word and a time-constant word—to establish mode, enable interrupts, and set operating parameters like prescaler values. The control word determines if the operation is in counter or timer mode, in addition to enabling channel interrupts and selecting other operational configurations. The timing mode sets the prescaler to divide the system clock either by 16 or 256, and the time constant word specifies the preset value in the down counter.

Operational Details

In timer mode, channels are triggered automatically and generate unique interrupt vectors. Timer intervals can be as brief as 2 µs (8 MHz), 3 µs (6 MHz), or 4 µs (4 MHz) without additional logic or software timing loops. Counting modes decrement on each CLK/TRG input pulse. The 44-pin configurations for the Z80 CTC include Dual Inline Package (DIP), Plastic Chip Carrier, and Quad Flat Pack—the latter is exclusive to CMOS versions.

Internal Architecture

The internal structure comprises four major components: the CPU bus I/O circuit for decoding address inputs, internal control logic for chip operating functions, interrupt control logic providing proper interface and priority control with the Z80 CPU interrupt system, and counter/timer circuits for operation handling. Importantly, the interrupt logic maintains the interrupt priority and system coherence.