Z85C35 CMOS ISCC Integrated Serial Communications Controller Data Sheet

Category: Electronics, Microprocessors Microcontrollers Peripheral ICS, Zilog

The Z85C35 CMOS ISCC is a serial communications controller featuring two separate SCC channels, each of which can operate independently at speeds of 0 to 4 Mbit/s in full-duplex mode. Each channel incorporates its crystal oscillator, baud rate generator, and digital phase-locked loop, which enables precise clock recovery. The device is software compatible with other Zilog CMOS SCC devices and supports a variety of data encoding formats including NRZ, NRZI, and FM.

Further enhancing its functionality, the Z85C35 is equipped with four DMA channels dedicated to transmitting and receiving data, and programmable for multi-protocol use. The DMA channels offer a sizable four gigabyte address range and an optimized flyby DMA transfer mode that boosts efficiency. This controller operates asynchronously, offering programmable bit lengths for character and error detection capabilities for parity, overrun, and framing errors.

With a Universal Bus Interface Unit, the Z85C35 interfaces seamlessly with most CPU types, including multiplexed or non-multiplexed bus architectures. It provides synchronous mode operation, which allows for internal or external character synchronization, CRC (Cyclic Redundancy Check) generation and checking in modes CRC-16 or CRC-CCITT. Moreover, the device supports SDLC/HDLC mode, granting extensive frame-level control which entails automatic zero insertion and deletion, |-field residue handling, and abort generation and detection.

General Description and Features

In terms of performance, the Z85C35’s advanced CMOS technology ensures low power consumption, high performance, and strong noise immunity. The ISCC (Integrated Serial Communications Controller) is a dual-channel, multi-protocol data communications peripheral compatible with most CPU interfaces. The ISCC stands out for its extensive internal register programming flexibility, which allows it to accommodate a broad range of serial communication applications with minimal need for external logic.

The ISCC’s DMA cell is specifically optimized for SDLC transfers and includes a 10 x 19-bit status FIFO to support high-speed operations. The device can handle up to four gigabytes of data per DMA channel, display 32-bit addresses, and prioritize between the four DMA channels to fit various applications. It can also function with both asynchronous and synchronous protocols such as Bisync and SDLC/HDLC, making it a versatile choice for various data transfer applications.

The 68-Pin PLCC Z85C35 effectively manages modem controls for serial communication, allowing for use in channels where such controls are essential. For system integration, it includes a universal bus interface catering to a wide variety of system/CPU structures, simplifying the implementation process. Finally, it incorporates a standard Zilog interrupt daisy chain for efficient interrupt hierarchy control, ranking the SCC cell with a higher priority over the DMA cell.