The IBMO436A4CBLBB, IBM0418A4CBLBB, IBMO436A8CBLBB, and IBMO418A8CBLBB are synchronous pipeline mode, high-performance CMOS static random access memories (SRAMs) with wide I/O and 3.0ns cycle times.
These SRAMs feature:
- Double data rate and single data rate synchronous modes of operation
- HSTL input and output levels
- Registered addresses, controls, and data inputs
- Burst mode of operation
- Common I/O
- Pipeline mode of operation
- Asynchronous output enable
- Self-timed late write with full data coherency
- Boundary scan using limited set of JTAG 1149.1 functions
- Single differential HSTL clock
- 9 x 17 Bump Ball Grid Array Package with SRAM JEDEC Standard Pinout and Boundary SCAN Order
- +2.5V Power Supply; Ground; 1.9V VDDQ; and 0.95V VREF
- Programmable impedance output drivers
Pin Description
The pinout includes address inputs, burst control starting addresses, data I/O, IEEE 1149.1 test inputs and output, differential echo clocks, HSTL input reference voltage, differential input register clocks, synchronous function control inputs, output power supply, and asynchronous output enable.
Ordering Information
The datasheet provides ordering information, including part numbers, organization, speed, and leads for different configurations.
Manual:
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