This datasheet describes a high-performance CMOS Static Random Access Memory (SRAM) with synchronous pipeline mode operation.
The SRAM is available in 8Mb (256Kx36 and 512Kx18) and 4Mb (128Kx36 and 256Kx18) organizations, with a cycle time of 3.0ns.
Key Features:
Double Data Rate and Single Data Rate Synchronous Modes
HSTL Outputs
Registered Addresses, Controls, and Data
Burst Mode of Operation
Common I/O
Pipeline Mode of Operation
Asynchronous Output Enable
Self-Timed Late Write with Full Data Coherency
Boundary Scan using limited set of JTAG 1149.1 functions
Single Differential Extended HSTL Clock
Package and Power Supply:
9 x 17 Bump Ball Grid Array Package with SRAM JEDEC Standard Pinout and Boundary SCAN Order
+2.5V Power Supply, Ground, 1.6V VDDQ, and 1.05V VREF
Manual:
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