This datasheet describes synchronous pipeline mode, high-performance CMOS static random access memories (SRAMs) with 8Mb (256Kx36 or 512Kx18) and 4Mb (128Kx36 or 256Kx18) organizations.
The SRAMs feature registered outputs, common I/O, and asynchronous output enable. They operate on a single +3.3V power supply and are compatible with HSTL I/O interfaces.
Key Features
The devices support synchronous pipeline mode of operation with self-timed late write, synchronous power down input, and single differential extended HSTL clock.
They also feature boundary scan using a limited set of JTAG 1149.1 functions, byte write capability, and global write enable.
The SRAMs are packaged in a 7 x 17 bump ball grid array (BGA) with an SRAM JEDEC standard pinout and boundary scan order.
Manual:
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