This datasheet describes high-performance synchronous pipeline mode SRAMs with 8Mb (256Kx36 and 512Kx18) and 4Mb (128Kx36 and 256Kx18) organizations.
Key features include:
Registered Outputs and Common I/O
0.25 micron CMOS technology and synchronous pipeline mode of operation with self-timed late write.
Power and Interface
Single differential HSTL clock, +2.5V power supply, and HSTL input and output levels.
Programmable Impedance Output Drivers
Output driver impedance can be adjusted using an external resistor (RQ) connected to the ZQ pin.
The SRAMs support byte write capability, global write enable, and asynchronous output enable and power down inputs.
They also feature boundary scan using a limited set of JTAG 1149.1 functions and are available in a 7 x 17 BGA package with SRAM JEDEC standard pinout and boundary scan order.
Manual:
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