Overview
The HCC40102B and HCC40103B are 8-stage presettable synchronous down counters available in 16-lead dual in-line plastic or ceramic packages.
Features
These counters have control inputs for enabling or disabling the clock, clearing the counter to its maximum count, and presetting the counter either synchronously or asynchronously.
All control inputs and the CARRY-OUT/ZERO-DETECT output are active-low logic.
Operation
In normal operation, the counter is decremented by one count on each positive transition of the CLOCK.
Counting is inhibited when the CARRY-IN/COUNTER ENABLE (CI/CE) input is high.
The CARRY-OUT/ZERO-DETECT (COZD) output goes low when the count reaches zero if the CI/CE input is low, and remains low for one full clock period.
When the SYNCHRONOUS PRESET-ENABLE (SPE) input is low, data at the JAM input is clocked into the counter on the next positive clock transition, regardless of the state of the CI/CE input.
When the ASYNCHRONOUS PRESET-ENABLE (APE) input is low, data at the JAM input is asynchronously forced into the counter, regardless of the state of the SPE, CI/CE, or CLOCK inputs.
Manual:
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