This datasheet specifies the 128Mb DDR SDRAM with a double-data-rate architecture, featuring two data transfers per clock cycle.
Key Features:
Four banks operation, differential clock inputs, and DLL aligns DQ and DQS transition with CK transition.
Read latency of 2, 2.5 (clock), burst length of 2, 4, 8, and burst type of sequential and interleave.
Ordering Information
Part numbers and maximum frequencies are provided, with options for 32M x 4, 16M x 8, and 8M x 16 configurations.
Interface and Package
SSTL2 interface, 66pin TSOP II package, and operating frequencies up to 166MHz.
Manual:
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