This datasheet describes synchronous pipeline mode, high-performance CMOS static random access memories (SRAMs) with 8Mb and 4Mb densities.
Key Features
The SRAMs have registered outputs, common I/O, and operate on a single +3.3V power supply. They also feature asynchronous output enable, synchronous pipeline mode of operation with self-timed late write, and synchronous power down input.
Package and Pinout
The devices are available in a 7 x 17 BGA package with SRAM JEDEC standard pinout and boundary scan order. The pinout includes address inputs, data I/O, clock mode inputs, and write enable pins.
The SRAMs are designed for high-performance applications, offering fast access times and cycle times.
Manual:
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