Description
The X4043/45 is a CPU supervisor device that integrates several key functions into a single package, thereby offering benefits such as reduced system cost, minimized board space, and improved reliability. It features Power-on Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock Protect Serial EEPROM Memory. The Power-on Reset Control ensures that the RESET signal is maintained while the power supply and oscillator stabilize after power-up. The Watchdog Timer helps in preventing failures by triggering a RESET when the microcontroller does not refresh the timer within a preset interval. This interval is selectable from three pre-set values and remains constant even after power cycling.
Low Vcc (voltage) detection circuitry is also included. It resets the system when supply voltage dips below the minimum Vcc trip point and maintains the RESET signal until acceptable voltage levels are reached and stable. This device can be programmed with custom Vcc threshold levels to accommodate unique requirements or to provide higher accuracy in sensitive applications.
Features
- Watchdog Timer: Selectable, ensures system reliability.
- Voltage Supervision: Asserts RESET when low Vcc is detected with five standard VTRIP thresholds and the option for custom programming.
- Power Efficiency:
– Low standby current: <2µA with watchdog on, <1µA with watchdog off.
– Active current: 3mA. - EEPROM Memory: 4kbits with a 16-byte page write mode and protection features to guard against unintentional writes during power-up/power-down events.
- Block Lock Protection: Provides multiple levels of EEPROM protection, including 0, 1/4, 1/2, all, or specific byte ranges.
- Communication Interface: Standard 400kHz 2-wire interface.
- Wide Operating Range: 2.7V to 5.5V power supply operation.
- Package Options: Available in 8 Ld SOIC, 8 Ld MSOP, and 8 Ld PDIP, with Pb-free plus anneal versions for RoHS compliance.
Block Diagram
The block diagram illustrates the internal structure, featuring a Watchdog Timer, Power-on and Low Voltage Reset Generation, RESET/RESET signal logic, EEPROM Array, and communication logic. A 2-wire interface is included for data transmission, represented by the SDA (Data Line) and SCL (Clock Line).
Caution: The X4043/45 devices are sensitive to electrostatic discharge; it is advised to practice proper integrated circuit handling procedures.
Manual:
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